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FPGA可编程逻辑器件芯片XC3S200A-5FGG320C中文规格书

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Chapter 2:Product Specification

Table 2-4:

LBUS Interface – RX Path Signals (Cont’d)

I/O

Domain

Description

Receive LBUS Empty for segment0. This bus indicates how many bytes of the RX_DATAOUT bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both RX_ENAOUT and RX_EOPOUT are sampled as 1. When RX_ERROUT and RX_ENAOUT are sampled as 1, the value of RX_MTYOUT[2:0] is always 000. Other bits of RX_MTYOUT are as usual.Receive LBUS Empty for segment1. Receive LBUS Empty for segment2. Receive LBUS Empty for segment3.

Name

RX_MTYOUT0[3:0]ORX_CLK

RX_MTYOUT1[3:0]RX_MTYOUT2[3:0]RX_MTYOUT3[3:0]

OOO

RX_CLKRX_CLKRX_CLK

Table 2-5:LBUS Interface – TX Path SignalsI/O

Domain

Description

Transmit LBUS Ready. This signal indicates whether the dedicated 100G Ethernet subsystem TX path is ready to accept data and provides back-pressure to the user logic. A value of 1 means the user logic can pass data to the 100G Ethernet subsystem. A value of 0 means the user logic must stop transferring data to the 100G Ethernet subsystem within four cycles or there will be an overflow.

If TX_RDYOUT goes to 0, it causes user logic to stop transferring data in the middle of a packet, and user logic must resume transferring data within 4 cycle of TX_RDYOUT returning to a value of 1.

Transmit LBUS Overflow. This signal indicates whether you have violated the back-pressure mechanism provided by the

TX_RDYOUT signal. If TX_OVFOUT is sampled as a 1, a violation has occurred. It is up to you to design the rest of the user logic to not overflow the TX interface. In the event of an overflow condition, the TX path must be reset.

Transmit LBUS Underflow. This signal indicates whether you have under-run the LBUS interface. If TX_UNFOUT is sampled as 1, a violation has occurred meaning the current packet is corrupted. Error control blocks are transmitted as long as the underflow

condition persists. It is up to the user logic to ensure a complete packet is input to the core without under-running the LBUS interface.

Transmit segmented LBUS Data for segment0. This bus receives input data from the user logic. The value of the bus is captured in every cycle that TX_ENAIN is sampled as 1.Transmit segmented LBUS Data for segment1.Transmit segmented LBUS Data for segment2.Transmit segmented LBUS Data for segment3.

Name

TX_RDYOUTOTX_CLK

TX_OVFOUTOTX_CLK

TX_UNFOUTOTX_CLK

TX_DATAIN0[127:0]TX_DATAIN1[127:0]TX_DATAIN2[127:0]TX_DATAIN3[127:0]

IIII

TX_CLKTX_CLKTX_CLKTX_CLK

Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021

Chapter 2:Product Specification

Table 2-7:

LBUS Interface – RX Path Control/Status Signals (Cont’d)Name

STAT_RX_FRAMING_ERR_VALID_4STAT_RX_FRAMING_ERR_VALID_5STAT_RX_FRAMING_ERR_VALID_6STAT_RX_FRAMING_ERR_VALID_7STAT_RX_FRAMING_ERR_VALID_8STAT_RX_FRAMING_ERR_VALID_9STAT_RX_FRAMING_ERR_VALID_10STAT_RX_FRAMING_ERR_VALID_11STAT_RX_FRAMING_ERR_VALID_12STAT_RX_FRAMING_ERR_VALID_13STAT_RX_FRAMING_ERR_VALID_14STAT_RX_FRAMING_ERR_VALID_15STAT_RX_FRAMING_ERR_VALID_16STAT_RX_FRAMING_ERR_VALID_17STAT_RX_FRAMING_ERR_VALID_18STAT_RX_FRAMING_ERR_VALID_19

I/O

OOOOOOOOOOOOOOOO

Domain

RX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLK

Description

Valid indicator for

STAT_RX_FRAMING_ERR_4[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_5[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_6[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_7[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_8[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_9[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_10[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_11[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_12[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_13[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_14[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_15[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_16[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_17[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_18[3:0]. Valid indicator for

STAT_RX_FRAMING_ERR_19[3:0]. This output is High when

STAT_RX_INTERNAL_LOCAL_FAULT or STAT_RX_RECEIVED_LOCAL_FAULT is asserted. This output is level sensitive.

STAT_RX_LOCAL_FAULTORX_CLK

Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021

Chapter 2:Product Specification

Table 2-7:

LBUS Interface – RX Path Control/Status Signals (Cont’d)Name

STAT_RX_PCSL_NUMBER_18[4:0]STAT_RX_PCSL_NUMBER_19[4:0]

I/O

OO

Domain

RX_CLKRX_CLK

Description

This signal indicates which PCS lane is received on physical lane 18.

This signal indicates which PCS lane is received on physical lane 19.

PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-multiplexed that PCS lane. These outputs are level sensitive.

Bad FCS indicator. A value of 1 indicates a packet was received with a bad FCS, but not a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

Stomped FCS indicator. A value of 1 or greater indicates that one or more packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to

indicate the stomped condition. Pulses can occur in back-to-back cycles.

Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding

CTL_RX_MAX_PACKET_LEN[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Pulses can occur in back-to-back cycles.

This signal goes High when an internal local fault is generated due to any one of the following: test pattern generation, bad lane alignment, or high bit error rate. This signal remains High as long as the fault condition persists.

This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. This signal remains High as long as the fault condition persists.

STAT_RX_PCSL_DEMUXED[19:0]ORX_CLK

STAT_RX_BAD_FCS[3:0]ORX_CLK

STAT_RX_STOMPED_FCS[3:0]ORX_CLK

STAT_RX_TRUNCATEDORX_CLK

STAT_RX_INTERNAL_LOCAL_FAULTORX_CLK

STAT_RX_RECEIVED_LOCAL_FAULTORX_CLK

Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021

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