Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.
Multichannel,24-Bit, 192 kHz, ⌺-⌬ DACAD1833AFUNCTIONAL BLOCK DIAGRAMDVDD1 DVZERO FLAGSAVDD2DDCDATAOUTLP1CLATCHSPIINTERPOLATORDACOUTLN1PORTCCLKINTERPOLATORDACOUTLP2OUTLN2MCLKRESETINTERPOLATORDACOUTLP3FILTEROUTLN3L/RCLKENGINEINTERPOLATORDACOUTRP3BCLKOUTRN3SDIN1DATAOUTRP2SDIN2PORTINTERPOLATORDACOUTRN2SDIN3INTERPOLATORDACOUTRP1SOUTOUTRN1AD1833ADGNDFILTR FILTDAGNDThe AD1833A is fully compatible with all known DVD formats,accommodating word lengths of up to 24 bits at sample rates of48kHz and 96 kHz on all six channels while supporting a 192kHzsample rate on two channels. It also provides the Redbook stan-dard 50ms/15 ms digital de-emphasis filters at sample rates of32kHz, 44.1kHz, and 48kHz.The AD1833A has a very flexible serial data input port thatallows glueless interconnection to a variety of ADCs, DSP chips,AES/EBU receivers, and sample rate converters. It can be con-figured in right-justified, left-justified, I2S, or DSP serial portcompatible modes. The AD1833A accepts serial audio data in MSBfirst, twos complement format. The AD1833A can be operatedfrom a single 5 V power supply; it also features a separate supplypin for its digital interface that allows it to be interfaced to devicesusing 3.3 V power supplies.The AD1833A is fabricated on a single monolithic integratedcircuit and is housed in a 48-lead LQFP package for operationfrom –40∞C to +85∞C.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 www.analog.comFax: 781/326-8703© 2003 Analog Devices, Inc. All rights reserved.
AD1833A–SPECIFICATIONSTEST CONDITIONS, UNLESS OTHERWISE NOTED*Supply Voltages (AVDD, DVDDX)Ambient TemperatureInput ClockInput SignalInput Sample RateMeasurement BandwidthWord WidthLoad CapacitanceLoad Impedance5V25∞C12.288 MHz, (8؋ Mode)Nominally 1 kHz, 0 dBFS(Full-Scale)48 kHz20 Hz to 20 kHz24 Bits100 pF10 kW*Performance is identical for all channels (except for the Interchannel GainMismatch and Interchannel Phase Deviation specifications).ParameterMinTypMaxUnitTest ConditionsANALOG PERFORMANCEDIGITAL-TO-ANALOG CONVERTERSDynamic Range (20 Hz to 20 kHz, –60 dBFS Input)with A-Weighted FilterAD1833AAAD1833AAAD1833ACTotal Harmonic Distortion + Noise106.5SNRInterchannel IsolationDC AccuracyGain ErrorInterchannel Gain MismatchGain DriftInterchannel Crosstalk (EIAJ Method)Interchannel Phase DeviationVolume Control Step Size (1023 Linear Steps)Volume Control Range (Max Attenuation) Mute AttenuationDe-emphasis Gain ErrorFull-Scale Output Voltage at Each Pin (Single-Ended)Output Resistance Measured DifferentiallyCommon-Mode Output VoltsDAC INTERPOLATION FILTER—8ϫ Mode (48 kHz)Pass BandPass-Band RippleStop BandStop-Band AttenuationGroup DelayDAC INTERPOLATION FILTER—4ϫ Mode (96 kHz)Pass BandPass-Band RippleStop BandStop-Band AttenuationGroup Delay110.0110.5107.0–95–94–95–94110108±30.280–120±0.10.098+63.5 (0.098)–63.5 (0.098)±0.11 (2.8)1502.2–dBdBdBdBdBdBdBdBdB%%ppm/∞CdBDegrees%dB (%)dB (%)dBV rms (V p-p)WVfS = 96 kHzTwo channels activeSix channels active96 kHz, two channels active96 kHz, six channels active±0.01247051021.768kHzdBkHzdBms37.7kHzdBkHzdBms±0.0355.03470160DAC INTERPOLATION FILTER—2ϫ Mode (192 kHz)Pass BandPass-Band RippleStop Band104.85Stop-Band Attenuation70Group Delay±1140.954kHzdBkHzdBms–2–
REV. 0
AD1833A
ParameterMinTypMaxUnitTest ConditionsDIGITAL I/OInput Voltage HIInput Voltage LOOutput Voltage HIOutput Voltage LOPOWER SUPPLIESSupply Voltage (AVDD and DVDD1)Supply Voltage (DVDD2)Supply Current IANALOGSupply Current IDIGITALPower Supply Rejection Ratio1 kHz 300 mV p-p Signal at Analog Supply Pins20 kHz 300 mV p-p Signal at Analog Supply PinsSpecifications subject to change without notice.2.40.8DVDD2–0.40.4538.5422–60–505.5DVDD14248VVVVVVmAmAmAdBdB4.53.3ActivePower-DownDIGITAL TIMING(Guaranteed over –40؇C to +85؇C, AV
ParameterMASTER CLOCK AND RESETtMLMCLK LO (All Modes)*MCLK HI (All Modes)*tMHtPDRPD/RST LOSPI PORTtCCHtCCLtCCPtCDStCDHtCLStCLHCCLK HI PulsewidthCCLK LO PulsewidthCCLK PeriodCDATA Setup TimeCDATA Hold TimeCLATCH SetupCLATCH HoldDD = DVDD = 5 V ؎ 10%)
Min15152020208010101010151510101015MaxUnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsComments24 MHz clock, clock doubler bypassed24 MHz clock, clock doubler bypassedTo CCLK risingFrom CCLK risingTo CCLK risingFrom CCLK risingDAC SERIAL PORTtDBHBCLK HIBCLK LOtDBLtDLSL/RCLK SetupL/RCLK HoldtDLHSDATA SetuptDDStDDHSDATA HoldTDM MODE MASTERtTMBDBCLKTDM DelayFSTDM DelaytTMFSDSDIN1 SetuptDStDHSDIN1 HoldTDM MODE SLAVEBCLKTDM FrequencyfTSBtTSBCHBCLKTDM HighBCLKTDM LowtTSBCLFSTDM SetuptTSFStTSFHFSTDM HoldSDIN1 SetuptTSDDStTSDDHSDIN1 HoldAUXILIARY INTERFACEtAXLRDL/RCLK DelaytAXDDData DelaytAXBDAUXBCLK Delay*MCLK symmetry must be better than 60:40 or 40:60.Specifications subject to change without notice.To BCLK risingFrom BCLK risingTo BCLK risingFrom BCLK risingFrom MCLK risingFrom BCLKTDM risingTo BCLKTDM fallingFrom BCLKTDM falling20101515256 ϫ fS202010101515101020nsnsnsnsnsnsnsnsnsnsnsnsnsTo BCLKTDM fallingFrom BCLKTDM fallingTo BCLKTDM fallingFrom BCLKTDM fallingFrom BCLK fallingFrom BCLK fallingFrom MCLK risingREV. 0
–3–
AD1833AtMHMCLKtMLPD/RSTtPDRFigure 1.MCLK and RESET TimingtCLSCLATCHtCCPtCCHtCCLtCLHCCLKtCDStCDHCIND15D14D9D8D0Figure 2.SPI Port TimingtDBHBCLKtDBLtDLSL/RCLKtDLHSDATALEFT-JUSTIFIEDMODEtDDSMSBMSB-1tDDHSDATAI2S MODEtDDSMSBtDDHSDATARIGHT-JUSTIFIEDMODEtDDSMSBtDDSLSBtDDHtDDHFigure 3.Serial Port TimingMCLK
tTMBDtTSBCLtTSBCHBCLKTDM
tTMFSDFSTDM
tTSFStTSFHtDStDHSDIN1MSBtTSDDStTSDDHFigure 4.TDM Master and Slave Mode Timing–4–
REV. 0
AD1833A
MCLKtAXBDAUXBCLKtAXLRDAUXL/RCLKtAXDDMSBAUX DATAFigure 5.Auxiliary Interface TimingABSOLUTE MAXIMUM RATINGS*(TA = 25∞C, unless otherwise noted.)AVDD, DVDDX to AGND, DGND . . . . . . . . –0.3 V to +6.5 VAGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 VDigital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 VAnalog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 VOperating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞CStorage Temperature Range . . . . . . . . . . . . –65∞C to +150∞CMaximum Junction Temperature . . . . . . . . . . . . . . . . 150∞CLQFP, qJA Thermal Impedance . . . . . . . . . . . . . . . . . 91∞C/WLead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability. Only one absolutemaximum rating may be applied at any one time.ORDERING GUIDEModelAD1833AASTAD1833ACSTEVAL-AD1833AEBAD1833AAST-REELAD1833ACST-REELTemperature Range–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞CPackage DescriptionLow Profile Quad Flat PackageLow Profile Quad Flat PackageEvaluation BoardLow Profile Quad Flat PackageLow Profile Quad Flat PackagePackage OptionST-48ST-48ST-48ST-48CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulateon the human body and test equipment and can discharge without detection. Although the AD1833Afeatures proprietary ESD protection circuitry, permanent damage may occur on devices subjected tohigh energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoidperformance degradation or loss of functionality.REV. 0
–5–
AD1833A
PIN CONFIGURATIONFILTDFILTRAGNDOUTRP3OUTRN3OUTRP2OUTRN236OUTRP135OUTRN134AVDD33AVDD32AGND31AGND30AGND29DGND28DVDD227RESET26ZERO1L25ZERO1R131415161718192021222324OUTLN2OUTLP2OUTLN3OUTLP34847454443424140393837OUTLP11OUTLN12AVDDAVDD43PIN 1IDENTIFIERAGND5AGND6AGND7DGND8DVDD19ZEROA10ZERO3R11ZERO3L12TOP VIEW(Not to Scale)AVDDAD1833ABCLKMCLKSDIN1SDIN2SDIN3ZERO2RCLATCHCDATAPIN FUNCTION DESCRIPTIONSPin No.123, 4, 33, 34, 445, 6, 7, 30, 31, 32, 418, 299101112131415161718192021222324252627283536373839MnemonicIN/OUTOUTLP1OUTLN1AVDDAGNDDGNDDVDD1ZEROAZERO3RZERO3LZERO2RCLATCHCDATACCLKL/RCLKBCLKMCLKSDIN1SDIN2SDIN3SOUTZERO2LZERO1RZERO1LRESETDVDD2OUTRN1OUTRP1OUTRN2OUTRP2OUTRN3OODescriptionDAC 1 Left Channel Positive Output.DAC 1 Left Channel Negative Output.Analog Supply.Analog Ground.Digital Ground.Digital Supply to Core Logic.Flag to Indicate Zero Input on All Channels.Flag to Indicate Zero Input on Channel 3 Right.Flag to Indicate Zero Input on Channel 3 Left.Flag to Indicate Zero Input on Channel 2 Right.Latch Input for Control Data (SPI Port).Serial Control Data Input (SPI Port).Clock Input for Control Data (SPI Port).Left/Right Clock for DAC Data Input; FSTDM Input in TDM Slave Mode;FSTDM Output in TDM Master Mode.Bit Clock for DAC Data Input; BCLKTDM Input in TDM Slave Mode; BCLKTDMOutput in TDM Master Mode.Master Clock Input.Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes).Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC inTDM Mode).Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode).Auxiliary I2S Output (Available in TDM Mode).Flag to Indicate Zero Input on Channel 2 Left.Flag to Indicate Zero Input on Channel 1 Right.Flag to Indicate Zero Input on Channel 1 Left.Power-Down and Reset Control.Power Supply to Output Interface Logic.DAC 1 Right Channel Negative Output.DAC 1 Right Channel Positive Output.DAC 2 Right Channel Negative Output.DAC 2 Right Channel Positive Output.DAC 3 Right Channel Negative Output.–6–
REV. 0
OOOOIIII/OI/OIII/OI/OOOOOIOOOOOSOUTZERO2LCCLKL/RCLKAD1833A
PIN FUNCTION DESCRIPTIONS (continued)Pin No.404243454748MnemonicIN/OUTOUTRP3FILTRFILTDOUTLP3OUTLN3OUTLP2OUTLN2ODescriptionDAC 3 Right Channel Positive Output.Reference/Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple toanalog ground.Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple to analog ground.DAC 3 Left Channel Positive Output.DAC 3 Left Channel Negative Output.DAC 2 Left Channel Positive Output.DAC 2 Left Channel Negative Output.OOOODEFINITION OF TERMSDynamic RangeGain ErrorThe ratio of a full-scale input signal to the integrated input noise inthe pass band (20 Hz to 20 kHz), expressed in decibels. Dynamicrange is measured with a –60 dB input signal and is equal to(S/[THD + N]) +60 dB. Note that spurious harmonics are belowthe noise with a –60 dB input, so the noise level establishes thedynamic range. The dynamic range is specified with and withoutan A-Weight filter applied.Signal to (Total Harmonic Distortion + Noise)[S/(THD + N)]With a near full-scale input, the ratio of actual output to expectedoutput, expressed as a percentage.Interchannel Gain MismatchWith identical near full-scale inputs, the ratio of outputs of thetwo stereo channels, expressed in decibels.Gain DriftChange in response to a nearly full-scale input with a change intemperature, expressed as parts-per-million (ppm/∞C).Crosstalk (EIAJ Method)The ratio of the root-mean-square (rms) value of the fundamentalinput signal to the rms sum of all other spectral components inthe pass band, expressed in decibels.Pass BandRatio of response on one channel with a grounded input to afull-scale 1 kHz sine wave input on the other channel, expressedin decibels.Power Supply RejectionThe region of the frequency spectrum unaffected by the attenuationof the digital decimator’s filter.Pass-Band RippleWith no analog input, signal present at the output when a300 mV p-p signal is applied to the power supply pins, expressedin decibels of full scale.Group DelayThe peak-to-peak variation in amplitude response from equal-amplitude input signal frequencies within the pass band, expressedin decibels.Stop BandThe region of the frequency spectrum attenuated by the digitaldecimator’s filter to the degree specified by stop-band attenuation.Intuitively, the time interval required for an input pulse to appearat the converter’s output, expressed in ms. More precisely, thederivative of radian phase with respect to the radian frequency ata given frequency.Group Delay VariationThe difference in group delays at different input frequencies.Specified as the difference between the largest and the smallestgroup delays in the pass band, expressed in ms.REV. 0
–7–
AD1833A–Typical Performance Characteristics
0.0100.0080.0060.0040.002Bd0–0.002–0.004–0.006–0.008–0.01000.20.40.60.81.01.21.41.61.82.0Hz؋104TPC 1.Pass-Band Response, 8ϫ Mode100–10–20–30B–40d–50–60–70–80–90–1002.002.052.102.152.202.252.302.352.402.452.50Hz؋104TPC 2.Transition Band Response, 8ϫ Mode0–20–40–60Bd–80–100–120–140–16000.51.01.52.02.53.0Hz؋105TPC 3.Complete Response, 8ϫ Mode0.100.080.060.040.02Bd0–0.02–0.04–0.06–0.08–0.1000.51.01.52.02.53.03.5Hz؋104TPC 4.Pass-Band Response, 4ϫ Mode0.50.40.30.20.1Bd0–0.1–0.2–0.3–0.4–0.500.51.01.52.02.53.03.54.0Hz؋104TPC 5.40 kHz Pass-Band Response, 4ϫ Mode100–10–20–30B–40d–50–60–70–80–90–1004.04.24.44..85.05.25.45.65.86.0Hz؋104TPC 6.Transition Band Response, 4ϫ Mode–8–
REV. 0
0–20–40–60Bd–80–100–120–140–16000.51.01.52.02.53.0Hz؋105TPC 7.Complete Response, 4ϫ Mode2.01.51.00.5Bd0–0.5–1.0–1.5–2.0012345678Hz؋104TPC 8.80 kHz Pass-Band Response, 2ϫ ModeREV. 0
AD1833A
100–10–20–30B–40d–50–60–70–80–90–1000.800.850.900.951.001.051.101.151.20Hz؋105TPC 9.Transition Band Response, 2ϫ Mode0–20–40–60Bd–80–100–120–140–16000.51.01.52.0Hz؋105TPC 10.Complete Response, 2ϫ Mode–9–
AD1833A
FUNCTIONAL DESCRIPTIONDevice ArchitectureThe AD1833A is a six-channel audio DAC featuring multibitsigma-delta (S-D) technology. The AD1833A features three stereoconverters (providing six channels); each stereo channel is con-trolled by a common bit-clock (BCLK) and synchronizationsignal (L/RCLK).General Overviewrate, only one doubling stage is used. In each case, the inputsample frequency is increased to 384 kHz (IMCLK/). TheZOH holds the interpolator samples for upsampling by themodulator. This is done at a rate 16 times the interpolatoroutput sample rate.ModulatorThe AD1833A is designed to run with an internal MCLK(IMCLK) of 24.576MHz and a modulator rate of 6.144MHz(i.e., IMCLK/4). From this IMCLK frequency, sample rates of48kHz and 96kHz can be achieved on six channels or 192kHzcan be achieved on two channels. The internal clock should neverbe run at a higher frequency but may be reduced to achievelower sampling rates, i.e., for a sample rate of 44.1 kHz, the appro-priate internal MCLK is 22.5792 MHz. The modulator rate scalesin proportion with the MCLK scaling.InterpolatorThe modulator is a 6-bit, second order implementation and usesdata scrambling techniques to achieve perfect linearity. The modu-lator samples the output of the interpolator stage(s) at arate of(IMCLK/4).OPERATING FEATURESSPI Register DefinitionsThe interpolator consists of as many as three stages of samplerate doubling and half-band filtering followed by a 16-samplezero order hold (ZOH). The sample rate doubling is achievedby zero stuffing the input samples, and a digital half-band filteris used to remove any images above the band of interest and tobring the zero samples to their correct values.The interpolator output must always be at a rate of IMCLK/.Depending on the interpolation rates selected, one, two, or allthree stages of doubling may be switched in. This allows forthree different sample rate inputs for any given IMCLK. For anIMCLK of 24.576 MHz, all three doubling stages are used witha 48 kHz input sample rate; with a 96 kHz input sample rate, onlytwo doubling stages are used; and with a 192 kHz input sampleThe SPI port allows flexible control of the device’s programmablefunctions. It is organized around nine registers: six individual channelvolume registers and three control registers. Each write operationto the AD1833A SPI control port requires 16 bits of serial datain MSB-first format. The four most significant bits are used toselect one of nine registers (seven register addresses are reserved),and the bottom 10 bits are written to that register. This allows awrite to one of the nine registers in a single 16-bit transaction. TheSPI CCLK signal is used to clock in the data. The incomingdata should change on the falling edge of this signal and remainvalid during the rising edge. At the end of the 16CCLK periods,the CLATCH signal should rise to latch the data internally intothe AD1833A (see Figure 2).The serial interface format used on the control port uses a 16-bitserial word, as shown in Table I. The 16-bit word is divided intoseveral fields: Bits 15 through 12 define the register address, Bits11and 10 are reserved and must be programmed to 0, and Bits9through 0 are the data field (which has specific definitions,depending on the register selected).Table I.Control Port MapRegister Address152141312NOTES1Must be programmed to zero.2Bit 15 = MSB.Reserved111109876Data Field543210Bit 150000000011111111Bit 140000111100001111Bit 130011001100110011Bit 120101010101010101Register FunctionDAC Control 1DAC Control 2DAC Volume 1DAC Volume 2DAC Volume 3DAC Volume 4DAC Volume 5DAC Volume 6DAC Control 3ReservedReservedReservedReservedReservedReservedReserved–10–
REV. 0
AD1833A
Table II.DAC Control Register 1 Address Reserved1De-emphasisSerial ModeFunctionData-WordWidthPower-DownRESETInterpolatorMode15–1200001101009–800 = None01 = 44.1 kHz10 = 32.0 kHz11 = 48.0 kHz7–5000 = I2S001 = RJ010 = DSP011 = LJ100 = Pack Mode 1 (256)101 = Pack Mode 2 (128)110 = TDM Mode111 = Reserved4–300 = 24 Bits01 = 20 Bits10 = 16 Bits11 = Reserved20 = Normal1 = PWRDWN1–000 = 8ϫ (48 kHz)201 = 2ϫ (192 kHz)210 = 4ϫ (96 kHz)211 = ReservedNOTES1Must be programmed to zero.2For IMCLK = 24.576 MHz.DAC CONTROL REGISTER 1De-emphasisDAC Word WidthThe AD1833A has a built-in de-emphasis filter that can be usedto decode CDs that have been encoded with the standardRedbook 50 ms/15 ms emphasis response curve. Three curves areavailable, one each for 32 kHz, 44.1 kHz, and 48 kHz samplingrates. The filters may be selected by writing to Control Bits 9and 8 in DAC Control Register 1 (see Table III).Table III.De-emphasis SettingsThe AD1833A will accept input data in three separate word-lengths—16 bits, 20 bits, and 24 bits. The word length may beselected by writing to Control Bits 4 and 3 in DAC ControlRegister 1 (see Table V).Table V.Word Length SettingsBit 40011Power-Down ControlBit 30101Word Length24 Bits20 Bits16 BitsReservedBit 90011Bit 80101De-emphasisDisabled44.1 kHz32 kHz48 kHzThe AD1833A can be powered down by writing to Control Bit 2in DAC Control Register 1 (see Table VI).Table VI.Power-Down ControlData Serial Interface ModeThe AD1833A’s serial data interface is designed to accept datain a wide range of popular formats including I2S, right-justified(RJ), left-justified (LJ), and flexible DSP modes. The L/RCLKpin acts as the word clock (or frame sync) to indicate sampleinterval boundaries. The BCLK defines the serial data ratewhile the data is input on the SDIN1–SDIN3 pins. The serialmode settings may be selected by writing to Control Bits 7through 5 in the DAC Control Register 1 (see Table IV).Table IV.Data Serial Interface Mode SettingsBit 201Interpolator ModePower-Down SettingNormal OperationPower-Down ModeBit 700001111Bit 600110011Bit 501010101Serial ModeI2SRight JustifyDSPLeft JustifyPacked Mode 1 (256)Packed Mode 2 (128)TDM ModeReservedThe AD1833A’s DAC interpolators can be operated in one ofthree modes—8ϫ, 4ϫ, or 2ϫ— then correspond to 48 kHz, 96kHz,and 192 kHz modes, respectively (for IMCLK = 24.576 MHz). Theinterpolator mode may be selected by writing to Control Bits 1and 0 in DAC Control Register 1 (see Table VII).Table VII.Interpolator Mode SettingsBit 10011Bit 00101Interpolator Mode8x (48 kHz)*2x (192 kHz)*4x (96 kHz)*Reserved*For IMCLK = 24.576 MHz.REV. 0
–11–
AD1833A
DAC CONTROL REGISTER 2DAC Control Register 2 contains individual channel mutecontrols for each of the six DACs. Default operation (bit = 0) ismuting off. Bits 9 through 6 of Control Register 2 are reservedand should be programmed to zero (see Table VIII).DAC CONTROL REGISTER 3Stereo ReplicateThe AD1833A allows the stereo information on Channel1(SDIN1—Left 1 and Right 1) to be copied to Channels 2 and3(Left/Right 2 and Left/Right 3). These signals can be used in anexternal summing amplifier to increase potential signal SNR.Stereo replicate mode can be enabled by writing to control Bit5(see TableXI). Note that replication is not reflected in the zeroflag status.Table VIII.DAC Control Register 2 Address15–120001Reserved*110100Reserved*9–605Channel 60 = Mute Off1 = Mute On43FunctionMute Control2Channel 30 = Mute Off1 = Mute On10Channel 5Channel 40 = Mute Off0 = Mute Off1 = Mute On1 = Mute OnChannel 2Channel 10 = Mute Off0 = Mute Off1 = Mute On1 = Mute On*Must be programmed to zero.Table IX.Muting ControlBit 5XXXXX1Bit 4XXXX1XBit 3XXX1XXBit 2XX1XXXBit 1X1XXXXBit 01XXXXXMutingMute Channel 1Mute Channel 2Mute Channel 3Mute Channel 4Mute Channel 5Mute Channel 6Table X.DAC Control Register 3FunctionAddress15–121000Stereo ReplicateReserved*Reserved*(192 kHz)1101009–6050 = Normal1 = ReplicateMCLK Select4–300 = IMCLK = MCLK ϫ 201 = IMCLK = MCLK ϫ 110 = IMCLK = MCLK ϫ 2/3Zero Detect20 = Active High1 = Active LowReserved*10 TDM Mode00 = Master1 = Slave*Must be programmed to zero.Table XI.Stereo ReplicateBit 501Stereo ModeNormalChannel 1 Data Replicated on Channels 2 and 3–12–
REV. 0
AD1833A
MCLK SelectThe AD1833A allows the matching of available external MCLKfrequencies to the required internal MCLK rate. The MCLKmodification factor can be selected from 2, 1, or 2/3 by writing toBit 4 and Bit 3 of Control Register 3. Internally, the AD1833Arequires an MCLK of 24.576 MHz for sample rates of 48 kHz,96 kHz, and 192 kHz. In the case of 48 kHz data with anMCLK of 256 ϫ fS, a clock doubler is used, whereas with anMCLK of 768 ϫ fS, a divide-by-3 block (Ϭ3) is first implementedfollowed by a clock doubler. With an MCLK of 512 ϫ fS, theMCLK is passed through unmodified (see Table XII).Table XII.MCLK Settingsa global zero flag that indicates all channels contain zero data.The polarity of the zero signal is programmable by writing toControl Bit 2 (see Table XIII). In right-justified mode, the sixindividual channel flags are best used as three stereo zero flagsby combining pairs of them through suitable logic gates. Then,when both the left and right inputs are zero for 1024 clock cycles,i.e., a stereo zero input for 1024 sample periods, the combinedresult of the two individual flags will become active, indicat-ing a stereo zero.Table XIII.Zero DetectBit 201Channel Zero StatusActive HighActive LowBit 40011Bit 30101Modification FactorMCLK ϫ 2 InternallyMCLK ϫ 1 InternallyMCLK ϫ 2/3 InternallyReservedDAC Volume Control RegistersChannel Zero StatusThe AD1833A provides individual logic output status indicatorswhen zero data is sent to a channel for 1024 or more consecutivesample periods in all modes except right-justified. There is alsoThe AD1833A has six volume control registers, one for each ofthe six DAC channels. Volume control is exercised by writing tothe relevant register associated with each DAC. This setting isused to attenuate the DAC output. Full-scale setting (all 1s) isequivalent to zero attenuation (see Table XV).Table XIV.MCLK vs. Sample Rate SelectionSampling RatefS (kHz)3212844.188.2176.446192Interpolator ModeRequired8ϫ4ϫ2ϫ8ϫ4ϫ2ϫ8ϫ4ϫ2ϫInternal MCLKRequired (MHz)16.384Suitable External MCLK Frequencies (MHz)MCLK ؋ 2MCLK ؋ 1MCLK ؋ 2/3819216.38424.57622.579211.2622.579233.868824.57612.28824.57636.8Table XV.Volume Control RegistersAddress15–12000000001111110011010101Reserved*110100Volume Control9–0Channel 1 Volume Control (OUTL1)Channel 2 Volume Control (OUTR1)Channel 3 Volume Control (OUTL2)Channel 4 Volume Control (OUTR2)Channel 5 Volume Control (OUTL3)Channel 6 Volume Control (OUTR3)*Must be programmed to zero.REV. 0
–13–
AD1833A
I2S TimingIS timing uses an L/RCLK to define when the data being trans-mitted is for the left channel and when it is for the right channel.The L/RCLK is low for the left channel and high for the rightchannel. A bit clock running at ϫ fS is used to clock in the data.There is a delay of 1 bit clock from the time the L/RCLK signalchanges state to the first bit of data on the SDINx lines. The datais written MSB first and is valid on the rising edge of the bit clock.Left-Justified Timing2to clock in the data. The first bit of data appears on the SDINxlines when the L/RCLK toggles. The data is written MSB firstand is valid on the rising edge of the bit clock.Right-Justified TimingLeft-justified (LJ) timing uses an L/RCLK to define when thedata being transmitted is for the left channel and when it is forthe right channel. The L/RCLK is high for the left channel andlow for the right channel. A bit clock running at ؋ fS is usedRight-justified (RJ) timing uses an L/RCLK to define when thedata being transmitted is for the left channel and when it is forthe right channel. The L/RCLK is high for the left channel andlow for the right channel. A bit clock running at ϫ fS is usedto clock in the data. The first bit of data appears on the SDINx8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJmode, the LSB of data is always clocked by the last bit clockbefore L/RCLK transitions. The data is written MSB first and isvalid on the rising edge of the bit clock.L/RCLKINPUTBCLKINPUTSDATAINPUTMSB–1MSB–2LEFT CHANNELRIGHT CHANNELMSBLSB+2LSB+1LSBMSBMSBMSB–1–2LSB+2LSB+1LSBMSBFigure 6.I 2S Timing DiagramL/RCLKINPUTLEFT CHANNELRIGHT CHANNELBCLKINPUTSDATAINPUTMSBMSB–1MSB–2LSB+2LSB+1LSBMSBMSB–1MSB–2LSB+2LSB+1LSBMSBMSB–1Figure 7.Left-Justified Timing DiagramL/RCLKINPUTBCLKINPUTSDATAINPUTLEFT CHANNELRIGHT CHANNELLSBMSBMSB–1MSB–2LSB+2LSB+1LSBMSBMSB–1MSB–2LSB+2LSB+1LSBFigure 8.Right-Justified Timing Diagram–14–
REV. 0
AD1833A
TDM Mode Timing—Interfacing to a SHARC®In TDM mode, the AD1833A can be the master or slave, depend-ing on Bit 0 in Control Register 3. In master mode, it generates aframe sync signal (FSTDM) on its L/RCLK pin and a bit clock(BCLKTDM) on its BCLK pin, whereas in slave mode it expectsthese signals to be provided. These signals are used to controlthe data transmission from the SHARC. The bit clock must runat a frequency of IMCLK/2 and the interpolation mode must beset to 8ϫ, which limits TDM mode to frequencies of 48 kHz orless. In this mode, all data is written on the rising edge of the bitclock and read on the falling edge of the bit clock. The framestarts with a frame sync at the rising edge of the bit clock. TheSHARC then starts outputting data on the next rising edge ofthe bit clock. Each channel is given a 32-bit clock slot, and thedata is left-justified and uses 16, 20, or 24 of the 32 bits. Anenlarged diagram detailing this is provided (see Figure 9). Thedata is sent from the SHARC to the AD1833A on the SDIN1pin and provided in the following order: MSB first—InternalDACL0, Internal DACL1, Internal DACL2, AUX DACL0,Internal DACR0, Internal DACR1, Internal DACR2, and AUXDACR0. The data is written on the rising edge of the bit clockand read by the AD1833A on the falling edge of the bit clock.The left and right data destined for the auxiliary DAC is sent instandard I2S format in the next frame using the SDIN2, SDIN3,and SOUT pins as the L/RCLK, BCLK, and SDATA pins,respectively, for communicating with the auxiliary DAC.DSP Mode TimingDSP mode timing uses the rising edge of the frame sync signalon the L/RCLK pin to denote the start of the transmission of adata-word. Note that for both left and right channels, a risingedge is used; therefore in this mode, there is no way to determinewhich data is intended for the left channel and which is intendedfor the right. The DSP writes data on the rising edge of BCLKand the AD1833A reads it on the falling edge. The DSP raisesthe frame sync signal on the rising edge of BCLK and then proceedsto transmit data, MSB first, on the next rising edge of BCLK.The data length can be 16, 20, or 24 bits. The frame sync signalcan be brought low any time at or after the MSB is transmitted,but must be brought low at least one BCLK period before thestart of the next channel transmission.FSTDMBCLKTDMINTERNALDAC L0INTERNALDAC L1INTERNALDAC L2AUXILIARYDAC L0INTERNALDAC R0INTERNALDAC R1INTERNALDAC R2AUXILIARYDAC R0BCLKTDM24-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSB+8LSB+7LSB+6LSB+5LSB+4LSB+3LSB+2LSB+1LSB20-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSB+4LSB+3LSB+2LSB+1LSB16-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSBFigure 9.TDM Mode TimingL/RCLKBCLKSDATAMSBMSB–1MSB–2MSB–3MSB–4MSB–5MSB–6MSBMSB–1MSB–2MSB–3MSB–4MSB–5MSB–6MSB32 BCLKs32 BCLKsFigure 10.DSP Mode TimingREV. 0
–15–
AD1833A
Packed Mode 128Packed Mode 256In Packed Mode 128, all six data channels are packed into onesample interval on one data pin. The BCLK runs at 128 ϫ fS;therefore, there are 128 BCLK periods in each sample interval.Each sample interval is broken into eight time slots: six slots of20 BCLK and two of 4 BCLK. In this mode, the data length isrestricted to a maximum of 20 bits. The three left channels arewritten first, MSB first, and the data is written on the fallingedge of BCLK. After the three left channels are written, there isa space of four BCLK, and then the three right channels are writ-ten. The L/RCLK defines the left and right data transmission; itis high for the three left channels and low for the three right channels.L/RCLKIn Packed Mode 256, all six data channels are packed into onesample interval on one data pin. The BCLK runs at 256 ϫ fS;therefore, there are 256 BCLK periods in each sample interval, andeach sample interval is broken into eight time slots of 32 BCLKeach. The data length can be 16, 20, or 24 bits. The three leftchannels are written first, MSB first, and the data is written on thefalling edge of BCLK with a one BCLK period delay from thestart of the slot. After the three left channels are written, there isa space of 32 BCLK, and then the three right channels are written.The L/RCLK defines the left and right data transmission; it islow for the three left channels and high for the three right channels.BCLKDATASLOT 1LEFT 0SLOT 2LEFT 1SLOT 3LEFT 2BLANK SLOT4 SCLKSLOT 4RIGHT 0SLOT 5RIGHT 1SLOT 6RIGHT 2BLANK SLOT 4 SCLKBCLKMSB–1MSB–2MSB–3MSB–4LSB+4LSB+3LSB+2LSB+120-BIT DATAMSBLSB16-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSBFigure 11.Packed Mode 128L/RCLKBCLKDATASLOT 1LEFT 0SLOT 2LEFT 1SLOT 3LEFT 2SLOT 4RIGHT 0SLOT 5RIGHT 1SLOT 6RIGHT 2BCLKMSB–1MSB–2MSB–3MSB–4LSB+8LSB+7LSB+6LSB+5LSB+4LSB+3LSB+2LSB+124-BIT DATAMSBLSB20-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSB+4LSB+3LSB+2LSB+1LSB16-BIT DATAMSBMSB–1MSB–2MSB–3MSB–4LSBFigure 12.Packed Mode 256–16–
REV. 0
AD1833A
011k⍀VOUT–11k⍀3.81k⍀270pFNPO68pFNPO–20–406OP2757604⍀VFILTOUT100pFNPO560pFNPO52.2nFNPOV1.50k⍀OUT+5.62k⍀5.62k⍀150pFNPOFigure 13.Suggested Output Filter Schematic0–20–40–60RBd–80–100–120–14002468101214161820kHzFigure 14.Dynamic Range for 1 kHz @ –60 dBFS,110 dB, Triangular Dithered Input0–20–40–60RBd–80–100–120–14002468101214161820kHzFigure 15.Input 0 dBFS @ 1 kHz, BW 20 Hz to20kHz, SR 48 kHz, THD + N –95 dBFSREV. 0
–60RBd–80–100–120–140020406080100120kHzFigure 16.Dynamic Range for 37 kHz @ –60 dBFS,110 dB, Triangular Dithered Input0–20–40–60RBd–80–100–120–140020406080100120kHzFigure 17.Input 0 dBFS @ 37 kHz, BW 20 Hz to120 kHz, SR 96 kHz, THD + N –95 dBFS0–20–40–60VBd–80–100–120–140–16002468101214161820kHzFigure 18.Noise Floor for Zero Input, SR 48 kHz,SNR 110 dBFS A-Weighted–17–
AD1833A
–60–70–80RBd–90–100–110–120–100–90–80–70–60–50–40–30–20–100dBFSFigure 19.THD + N Amplitude vs. Input Amplitude,Input 1 kHz, SR 48 kHz, 24-Bit–20–30–40–50–60RBd–70–80–90–100–110–120–100–90–80–70–60–50–40–30–20–100dBFSFigure 20.THD + N Ratio vs. Input Amplitude,Input 1kHz, SR 48 kHz, 24-Bit–18–
REV. 0
AD1833A
DVDD–INTF5V10F10F0.1F10F0.1F0.1F0.1F10FDVDD0.1FAVDD10FCLATCHCDATACCLK26SDATA11FSYNC12SCK19MCKM0M1M2M3CUCBLVERFERF23241817114152825654322716130.1F928DVDD1DVDD214CLATCH15CDATA16CCLK17182021222319L/RCLKBCLKSDIN1SDIN2SDIN3SOUTMCLK43333444AVDD1AVDD2AVDDAVDDAVDD1OUTLP12OUTLN147OUTLP2OUTLN24845OUTLP3OUTLN34636OUTRP135OUTRN138OUTRP237OUTRN240OUTRP3OUTRN339GNDGNDGNDFILTRFILTD4243+10F0.1F+10FL1+L1–L2+L2–L3+L3–R1+R1–R2+R2–R3+R3–
10F10F0.1F0.1F10FAVDD5V22VA+10nF75RO10nF10201k⍀RXNFILT9RXP7VD+PALAD1833ADIR-CS8414DGND1DGND2GNDGND47nF218AGNDDGNDGNDGNDCO/EOCA/E1CB/E2CC/F0CD/F1CE/F2SELCS12/FCK829730631532410.1F++++++5VL535624SHLD1SHLD1SHLD1SHLD1DVDD+10k⍀0.1FU5TORX173OUT1Figure 21.Example Digital InterfaceREV. 0
–19–
AD1833A
OUTLINE DIMENSIONS48-Lead Low Profile Quad Flat Package [LQFP]1.4 mm Thick(ST-48)Dimensions shown in millimeters1.60 MAX0.75INDICATORPIN 10.609.00 BSC 0.454837136SEATING 1.45PLANE 1.40 0.20TOP VIEW7.00 1.35 0.09(PINS DOWN)BSC7؇VIEW A3.5؇0.150؇12250.05SEATINGPLANE0.08 MAX1324COPLANARITYVIEW A0.50 0.27ROTATED 90؇ CCWBSC 0.22 0.17COMPLIANT TO JEDEC STANDARDS MS-026BBC–20–)0(30/5–0–63320CREV. 0
因篇幅问题不能全部显示，请点此查看更多更全内容
Copyright © 2019- baomayou.com 版权所有 赣ICP备2024042794号-6
违法及侵权请联系：TEL:199 18 7713 E-MAIL:2724546146@qq.com
本站由北京市万商天勤律师事务所王兴未律师提供法律服务