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专利名称：Shift register circuit and display device发明人：小倉 潤申请号：JP2019028404申请日：20190220公开号：JP2020135910A公开日：20200831
专利附图：
摘要：Problem to be solved: to provide a shift register circuit and a display devicewhich stably control the circuit scale and operate stably. Shift register circuit SRNA circuitfor outputting an output signal from a first output terminal and a second output terminalbased on a clockClock input terminal to which clock is inputSource is the first output
terminal andThe output tfttm 3 connected to the clock input terminalGate is the gate ofthe output TFTThe source is the second output terminal andThe transfer TFTM 3B whosedrain is connected to the drain of the output TFT isThe first node an connected to thegate of the output TFT and the gate of the transfer TFTA bootstrap capacitor CBTconnected between the gate and source of the transfer TFTA first input terminal to whicha signal for switching the voltage of the first node to a high voltage is inputA secondinput terminal to which a signal for switching the voltage of the first node to a lowvoltage is input.Diagram
申请人：凸版印刷株式会社
地址：東京都台東区台東１丁目５番１号
国籍：JP
代理人：蔵田 昌俊,野河 信久,河野 直樹,井上 正,飯野 茂,金子 早苗
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