3-8译码器 ........................................................................................................................................ 2 D触发器 ........................................................................................................................................... 3 加法器 .............................................................................................................................................. 3 计数器 .............................................................................................................................................. 4
-- An enable up/down counter ................................................................................................... 4 -- A synchronous load counter................................................................................................... 5 -- A synchronous clear load enable counter .............................................................................. 5 寄存器 .............................................................................................................................................. 6 数据选择器....................................................................................................................................... 6
3-8译码器
LIBRARY IEEE; -- 3-8译码器 USE IEEE.STD_LOGIC_11.ALL; ENTITY decode_3to8 IS
PORT(a,b,c,G1,G2A,G2B: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decode_3to8;
ARCHITECTURE rtl OF decode_3to8 IS
SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN
indata<=c & b & a;
PROCESS(indata,G1,G2A,G2B) BEGIN
IF(G1='1' AND G2A='0' AND G2B='0') THEN CASE indata IS
WHEN \"000\"=>y<=\"11111110\"; WHEN \"001\"=>y<=\"11111101\"; WHEN \"010\"=>y<=\"11111011\"; WHEN \"011\"=>y<=\"11110111\"; WHEN \"100\"=>y<=\"11101111\"; WHEN \"101\"=>y<=\"11011111\"; WHEN \"110\"=>y<=\"10111111\"; WHEN \"111\"=>y<=\"01111111\";
WHEN OTHERS=>y<=\"XXXXXXXX\"; END CASE; ELSE
y<=\"11111111\"; END IF;
END PROCESS; END rtl;
D触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY d_ff IS
PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ; nq : OUT STD_LOGIC); END ENTITY d_ff;
ARCHITECTURE a_rs_ff OF d_ff IS BEGIN
PROCESS(CLK) BEGIN
IF clk = '1' AND clk'EVENT THEN q <= d ; nq <= NOT d; END IF; END PROCESS; END a_rs_ff;
加法器
LIBRARY ieee;
USE ieee.std_logic_11.all; USE ieee.std_logic_arith.all; ENTITY adder IS PORT (op1, op2 : IN UNSIGNED(7 downto 0); result : OUT INTEGER); END adder;
ARCHITECTURE maxpld OF adder IS BEGIN result <= CONV_INTEGER(op1 + op2); END maxpld;
LIBRARY ieee;
USE ieee.std_logic_11.all; USE ieee.std_logic_arith.all;
USE ieee.std_logic_UNSIGNED.all; ENTITY adder IS
PORT (op1, op2 : IN INTEGER range 0 to 255; result : OUT INTEGER range 0 to 511); END adder;
ARCHITECTURE maxpld OF adder IS BEGIN result <= op1 + op2; END maxpld;
计数器
LIBRARY ieee;
USE ieee.std_logic_11.all; USE ieee.std_logic_arith.all;
USE ieee.std_logic_UNSIGNED.all; ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; q : OUT INTEGER RANGE 0 TO 255;); END counters;
ARCHITECTURE a OF counters IS BEGIN
-- An enable up/down counter
PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = '1') THEN direction := 1; ELSE direction := -1; END IF; IF (clk'EVENT AND clk = '1') THEN IF enable = '1' THEN cnt := cnt + direction; END IF;
END IF; q <= cnt; END PROCESS;
-- A synchronous load counter
PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clk'EVENT AND clk = '1') THEN IF ld = '0' THEN cnt := d; ELSE cnt := cnt + 1; END IF; END IF; qb <= cnt; END PROCESS;
-- A synchronous clear load enable counter
PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clk'EVENT AND clk = '1') THEN IF clear = '0' THEN cnt := 0; ELSE IF ld = '0' THEN cnt := d; ELSE IF enable = '1' THEN cnt := cnt + 1; END IF; END IF; END IF; END IF; qk <= cnt; END PROCESS; END a;
寄存器
LIBRARY ieee;
USE ieee.std_logic_11.all; USE ieee.std_logic_arith.all;
USE ieee.std_logic_UNSIGNED.all;
ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk : IN BIT; q : OUT BIT_VECTOR(11 DOWNTO 0)); END reg12;
ARCHITECTURE a OF reg12 IS BEGIN PROCESS BEGIN WAIT UNTIL clk = '1'; q <= d; END PROCESS; END a;
数据选择器
ENTITY selsig IS PORT ( d0, d1, d2, d3 : IN BIT; s : IN INTEGER RANGE 0 TO 3; output : OUT BIT ); END selsig;
ARCHITECTURE maxpld OF selsig IS BEGIN
WITH s SELECT -- creates a 4-to-1 multiplexer output <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3; END maxpld;
