LIBRARY IEEE

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY qicheweideng IS

PORT(CLK,LEET,RIGHT,BRAKE,NIGHT,LP,LR:IN STD_LOGIC;

CP,LP,RP,LR,BRAKE,LED,NIGHT_LED,LEDL,LEDB,LEDN:OUT STD_LOGIC);

ARTHITECTURE ART OF SZ IS

SIGNAL COUNT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN COUNT<=COUNT+1; END IF;

END PROCESS;

CP<=COUNT(3); END ART;

ARCHITECTURE ART OF CTRL IS BEGIN

NIGHT_LED<=NIGHT; BRAKE_LED<=BRAKE; PROCESS(LEFT,RIGHT)

VARIABLE TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN

TEMP:=LEFT&RIGHT; CASE TEMP IS

WHEN \"00\"=>LP<='0';RP<='0';LR<='0'; WHEN \"01\"=>LP<='0';RP<='1';LR<='0'; WHEN \"10\"=>LP<='1';RP<='0';LR<='0';

WHEN OTHERS=>LP<='0';RP<='0';LR<='1'; END CASE; END PROCESS; END ART;

ARCHITECTURE ART OF LC IS BEGIN

LEDB<=BRAKE; LEDN<=NIGHT;

PROCESS(CLK,LP,LR)

BEGIN

IF CLK'EVENT AND CLK='1' THEN IF (LR='0') THEN IF(LP='0') THEN LEDL<='0'; ELSE

LEDL<='1'; END IF; ELSE

LEDL<='0'; END IF; END IF;

END PROCESS; END ART;

ARCHITECTURE ART OF RC IS BEGIN

LEDB<=BRAKE; LEDN<=NIGHT;

PROCESS(CLK,RP,LR) BEGIN

IF CLK'EVENT AND CLK='1' THEN IF (LR='0') THEN IF(RP='0') THEN LEDR<='0'; ELSE

LEDR<='1'; END IF; ELSE

LEDR<='0'; END IF; END IF;

END PROCESS; END ART;