900MHzCMOS锁相环频率综合器英文

半　导　体　学　报

CHINESEJOURNALOFSEMICONDUCTORS

.24,No.12Vol

Dec.,2003

A900MHzCMOSPLL󰃗FrequencySynthesizer

3

InitializationCircuit

ZhaoHui,RenJunyanandZhangQianling

(ASICandSystemStateKeyLaboratory,FudanUniversity,Shanghai　200433,China)

Abstract:A900MHzCMOSPLL󰃗frequencysynthesizerusingcurrent2adjustablecharge2pumpcircuitandon2chiploopfilterwithinitializationcircuitispresented.Thecharge2pumpcurrentisinsensitivetothechangesoftempera2tureandpowersupply.Thevalueofthecharge2pumpcurrentcanbechangedbyswitches,whicharecontrolledby.ThustheperformanceofthePLL,suchasloopbandwidth,canbechangedwiththechangeoftheexternalsignals

charge2pumpcurrent.TheloopfilterinitializationcircuitcanspeedupthePLLwhenthepowerison.Amulti2mod2.Thecircuitisdesignedusing0118Λulusprescalerisusedtofulfillthefrequencysynthesism,118V,1P6Mstandard.digitalCMOSprocess

Keywords:PLL;charge2pump;loopfilter;multi2modulusprescalerEEACC:2570

CLCnumber:TN43112　　　Documentcode:A　　　ArticleID:025324177(2003)1221244206

ture;alsointheon2chipfilter,aninitializationcir2

1　Introduction

Phase2lockedloops(PLLs)arewidelyusedin.communicationapplications

Theycan

recover

cuitisaddedintospeedupthePLLwhenpowerison.

2　Charge-pumpPLL

Acharge2pumpPLL

[1]

clockfromreceiveddatasignals,performfrequencyandphasemodulation󰃗demodulation,andfrequency.Nowadays,especiallyinwirelesscommu2synthesis

nicationsystems,frequencysynthesizersmainlytakethePLL2basedstructure,andcharge2pump[1]

PLL(CPPLL)isthemostpopulararchitecture.

Inthiswork,wepresentaPLL󰃗frequencysynthesizercircuitwhosecharge2pumpcurrentcanbeadjusted,andtheoutputpumpcurrentisinsen2sitivetothechangesofpowersupplyandtempera2

3ProjectsupportedbyShanghaiAppliedMaterialFund(No.0102)

　ZhaoHui　male,wasbornin1969,PhDcandidate.HiscurrentresearchinterestsareCMOSanalogandRFfront2endintegratedcircuitsde2

sign.

consistsofseveralma2

jorblocksincludingaphase2frequencydetector,acharge2pumpandaloopfilter,avoltage2controlledoscillator,andaprescaler,whichisoptional,inthefeedbackloop.

Withinalimitedranges,aPLLcanbemodeledasalineartransferfunction.Figure1showsagenericlinearmodelofaPLL

[2,3]

.

Inabovemodel,theVCOactsasanidealinte2

　RenJunyan　male,wasbornin1960,professor.HiscurrentresearchinterestsarethedesignofRFfront2endsystemsandcircuitsandcom2

putercommunicationcircuits.

　ZhangQianling　female,wasbornin1936,professor,adviserofPhDcandidates.Hercurrentresearchfieldsinvolvemicroelectronics,system2

on2chipdesign.

　Received2May2003,revisedmanuscriptreceived4July2003c2003TheChineseInstituteofElectronics○

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　12期ZhaoHuietal.:　A900MHzCMOSPLL󰃗FrequencySynthesizerInitialization…1245

(Ns)withs=jΞ,onecanfindHo(s)=KpdH(s)Kv󰃗

outwhatthebandwidthofthesystemΞbiswhen

󰃜Ho(jΞ)󰃜equalsto1.Theresultisthattheband2widthofthesystemisproportionaltothechargepumpoutputcurrent.Andthesettlingtimeap2

Fig.1　AgenericlinearmodelforPLL

[5]

󰃗proximatesto-lnΕΞb,whereΕrepresentsthe

settlingaccuracy.Thus,ifthecharge2pumpcurrentcanbechangedduringoperation,thentheperfor2mancesofthePLLcanbechangedalso.

gratorofphaseandtheoutputphasecanexpressedas

KK

∫

0

v

t

c

(t)dt+3　CPPLLcircuitdesign

Asmentionedinsection2,thecharge2pumpcurrentisakeyfactorinfluencingtheperformancesoftheCPPLLsuchasthebandwidth,thetrackingspeed,andthenoiseperformancesofthePLL.

Thearchitectureofthedesignedcharge2pumpPLLcircuitisshowninFig.2.

whereΞcrepresentsthenominalVCOfrequencyinradianspersecond,andKvrepresentstheVCOgaininradianspersecondpervolt.Thephasede2tectoroutputisgivenby

Vd=Kpdf((2)(3)

where

backdividerratio.

whichistheloopphaseerror,andNisthefeed2

Asforacharge2pumpPLL,theoutputcurrentofthecharge2pumpcanbeexpressedas

ip=Ipsgn(Σ)

[1,4]

(4)

whereIpisthereferencecurrentofthecharge2pump,ΣisthetimeintervalofUP󰃗DOWNsignals,whosevalueisdeterminedbyThenthePFDgainKpdisproportionaltothecharge2pumpoutputcurrentandthetimeintervaloftheUP󰃗DOWNsignalsandcanbeexpressedas

(5)Kpd=Vd󰃗f((s)Vc=VdH(s)=ipZ(s)H(s)=ipH′loopfilter.

FromFig.1,wecanwritetheclosedlooptransferfunctionas

(6)

Fig.2　BlockdiagramofthedesignedCPPLL

311　Powersupplygenerator

Becausethecharge2pumpcurrentisakeypa2rameterinthedesignofPLLsorfrequencysynthe2sizers,itshouldbeinsensitivenotonlytothechangesofpowersupplyandtemperature,butalsotothepowersupplynoise.Thepowersupplygen2eratorisusedheretogenerateasupplyvoltage

[6]

with118Vforanalogpart.

whereH(s)representsthetransferfunctionofthe

312　Charge-pumpcircuit

Thecharge2pumpcircuitconsistsofacurrent

KpdH(s)Kv󰃗s1+

1N

(7)

KpdH(s)Kv󰃗s

[6]

referencecircuitandacurrentoutputcircuit.ThedesigninRef.[6]isshowninFig.3(a),thecur2

Takingtheabsolutevalueoftheopenloopgain

rentgeneratedbycurrentreferencecircuitismir2

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1246半　导　体　学　报24卷　

roredtothecurrentoutputcircuitandsourcescur2renttoorsinkscurrentfromtheloopfilteraccord2ingtothesignalsUPandDOWN.Thecurrentmir2roredtothecurrentoutputcircuitcanbeadjustedthroughthebranchesMN2,MN3,andMN4con2.TheswitchunderMN1isal2trolledbyswitches

.waysoninordertomatchtheotherswitches

Butthereisadrawbackintheabovestruc2ture,thatiswhetherMN2,MN3and󰃗orMN4sinkcurrentornot,thetotalcurrentdrawfromthepowersupplythroughMP1isfixedwiththemaxi2mumvalue.ThussomeextrapowerisdissipatedwhenswitchesS2,S3,orS4areon.

TheimprovedstructureisshowninFig.3(b).WhenswitchesS2,S3,andS4areoff,thereisnomoreextracurrentdrawnfrompowersupply,andthennomorepowerisdissipated.

voltageoftheloopfilteriszero.IfadownsignalofPFDisfirstgeneratedafterthepoweron,theout2putcontrolvoltageoftheloopfiltershouldde2crease,butthevoltagevaluecannotgodownbelowzero.Soaninitializationcircuitisaddedtotheloop

filter(seeFig.4).ASchmittflip2flopwithtwothresholdvoltagesof015Vand0195Visusedtosensethecontrolvoltageontheloopfilter.Whenthepoweron,apulsesignalRESETisgenerated,INITsignalisactive,loopfilterisinitializedbyMN1,MN2,andMP1.Whenthecontrolvoltagereaches0195V(abouthalfofthepowersupply),Schmittflip2flop

toggles,then

theoutputof

Schmittflip2flopdisablestheinitializationopera2tioneventhoughRESETishigh.Thisconfigura2tioncanspeedupthePLLsystem.

Fig.4　Loopfilterwithinitializationcircuit

314　Multi-modulusprescaler

Toachievehigh2speedandlow2powerdesign,itisdesirabletominimizetheamountofcircuitryoperatingathighfrequency.Basedontraditionaldual2modulus

prescaler

[7～9]

,amulti2modulus

prescalerisdesignedasshowninFig.5(a),which3counterasconsistsofasynchronousdivide2by22󰃗thefirststage.

Fig.3　Chargepumpcircuitstructure　(a)ChargepumpcircuitstructureinRef.[6];(b)Improvedchargepumpcircuitstructure

stage,anasynchronousdivide2by232

counterasthesecondstage,andacontrolledlogic

Theoperationofthecontrolledlogicisex2plainedasfollow.WhenD3～D0arezerosandthenMCisone,thefirststagedoesdivide2by22only,andthetotaldivisionratiois.ThesignalYiisdeterminedbytheoutputsofF3,F4,F5,andF6(thetimingdiagramisshowninFig.5(b)).The

313　Loopfilterwithinitializationcircuit

Whenthepowerisoff,theoutputcontrol

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　12期ZhaoHuietal.:　A900MHzCMOSPLL󰃗FrequencySynthesizerInitialization…1247

isgivenby

N=+D3×2+D2×2+D1×2+D0×2

3

2

1

0

(8)

315　OthercircuitsoftheCPPLL

TheVCOisaringoscillator,whichismadeupofafour2stagecross2coupleddifferentialdelay

cells,buffers,andD2S(differentialtosingle)cir2cuit.ThePFDusedinthisworktakestheformde2scribedinRef.[10].

4　Experimentalresults

Thewholecharge2pumpPLLcircuitwasde2signedusingSMIC0118Λm118VstandarddigitalCMOSprocess.Thecircuitwassimulatedusingtypical,fast,andslowmodels.ThesimulationtoolisHspice.

Thepowersupplygeneratorwassimulatedwiththetemperaturesweptfrom0℃to100℃,andthepowersupplyvoltagesweptfrom1144Vto2116V(20%changesinVDD)duringsimulation.Theoutputvoltageisabout118Vandchangeslit2

[6]tle.

Thecurrentofthecharge2pumpreferencecir2cuitwassimulatedsweptfrom0℃to100℃with

Fig.5　Multi2modulusprescaler　(a)Multi2modu2lusprescalerblockdiagram;(b)Timingdiagramoftheprescaler

i

signalYigeneratesasignalpulsewith22clockcy2

switchesonoroff,theoutputcurrentcanbechangedfrom715ΛAto82ΛA,andthetemperaturecoefficientoftheoutputcurrentat25℃isabout+0102%change󰃗℃or+200ppm󰃗℃.

TheVCOcanbetunedfrom800MHzto980MHz,thecontrolvoltageisfrom0175Vto1145V.

Then,thewholePLLissimulated.TheoutputcontrolvoltageoftheloopfilterisshowninFig.6.Therearetworesultsforchargepumpcurrentwiththevalueof82ΛA,oneisfor827MHzoutputfrequencyandtheotherisfor961MHzoutputfre2quencyoftheVCO.Alsoshowninthefigureisan2otheranalysiswiththechargepumpcurrentvalueof47ΛA.TheFFTanalysisisshowninFig.7.

Accordingtotheanalysisinsection2,thebandwidthofthePLLsystemisoneofthemost

clein16clockcyclesofX2,whichistheoutputofthefirstdivisionstage,andisnon2overlappedeachother.Z0isthecombinedcycleofnclocksaccord2ingtoDi,wheren=D3×2+D2×2+D1×2+D0.CombinedwiththesignalZ1,whichisone2fourthof322clockcycleofX2,MCgeneratesazerosignalpulseofnclocksinthis322clockcycleandasingleclockperiodofINisswallowed.Thismakesthe

firststageasadivide2by23divider(seeX2′inFig.5(b)),thustheprescalerfunctionsasadivide2by2(+n)divider.Afterwardthedivide2by22actionisresumed.Therefore,theprescaler’sdivisionratio

3

2

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1248半　导　体　学　报24卷　

Fig.6　TransientanalysisofthecontrolvoltageforVCOofPLL

Fig.8　ChipphotoofthedesignedPLL

thetemperature.Apowersupplygeneratorisusedtogeneratethesupplyvoltagefortheanalogcir2cuits;thisgeneratedvoltageisinsensitivetothechangesofthetemperatureandpowersupply.Andthustheoutputpumpcurrentofthecharge2pumpcircuitisalsoinsensitivetothechangesofpowersupply.Aninitializationcircuitisaddedtotheon2chiploopfiltertospeedupthePLLwhenpowerison.Thewholecircuitwasdesignedusing0118Λm

Fig.7　FFTanalysisofthePLL

118VstandarddigitalCMOSprocess,andthesim2ulationresultsshowthattheperformanceofthecircuitissatisfied.References

[1]　GardnerFM.Charge2pumpphase2lockloops.

Commun,1980,28(11):1849

[2]　WolaverDH.

Hall,Inc,1991

[3]　CrawfordJA.

Frequencysynthesizerdesignhandbook.

ArtechHouse,Inc,1994

[4]　VanPaemelM.Analysisofacharge2pumpPLL:anewmod2

.IEEETransCommun,1994,42(7):2490el

[5]　CraninckxJ,SteyaertMSJ.WirelessCMOSfrequencysyn2

thesizerdesign.KluwerAcademicPublishers,1998

[6]　ZhaoHui,XuDonglin,PanSha,etal.ThedesignofaCMOS

current2adjustablecharge2pumpcircuitinsensitivetopowersupplyandtemperature.ChineseJournalofSemiconductors,2003,24(3):260

[7]　ForoudiN,KwasniewskiTA.CMOShigh2speeddual2modu2

lusfrequencydividerforRFfrequencysynthesis.IEEEJSol2id2StateCircuits,1995,30(2):93

Phase2lockedloopcircuitdesign.

Prentice2IEEETrans

importantperformanceanditsvalueisproportionaltothecharge2pumpcurrent,andthetransientchar2acteristicsofthePLLsuchassettlingtimeisafunctionofthebandwidth,thatiswiththelargerbandwidth,thesettlingtimeisshorter.Fromthesimulationresult,itcanbeseenthatthedesignverifiestheanalysisinsection2,andthedesignideausingthecurrent2adjustablecharge2pumpcir2cuittochangetheperformanceofthePLLisappli2cable.

Figure8showsthechipphotoofthedesignedPLL.

5　Conclusion

Inthiswork,a900MHzcharge2pumpPLLwithadjustablepumpcurrentandon2chiploopfil2terispresented.Theoutputreferencepumpcur2rentisdesignedtobeinsensitivetothechangesof

© 1995-2006 Tsinghua Tongfang Optical Disc Co., Ltd. All rights reserved.

　12期ZhaoHuietal.:　A900MHzCMOSPLL󰃗FrequencySynthesizerInitialization…

StateCircuits,1996,31(7):0

1249

[8]　LarssonP.High2speedarchitectureforaprogrammablefre2

quencydividerandadual2modulusprescaler.IEEEJSolid2StateCircuits,1996,31(5):744

[9]　CraninckxJ,SteyaertM.A1175GHz󰃗3Vdual2modulusdi2

129prescalerin017Λvide2by2128󰃗mCMOS.IEEEJSolid2

[10]　VonKaenelV,AebischerD,PiguetC,etal.A320MHz,

115mW@1135VCMOSPLLformicroprocessorclockgener2ation.IEEEJSolid2StateCircuits,1996,31(11):1715

900MHzCMOS锁相环󰃗频率综合器3

赵　晖　任俊彦　章倩苓

(复旦大学专用集成电路与系统国家重点实验室,上海　200433)

摘要:给出了一个900频率综合器的设计,设计中采用了电流可变电荷泵及具有初始化电路的MHzCMOS锁相环󰃗环路滤波器.电荷泵电流对温度与电源电压变化的影响不敏感,同时电流的大小可通过外部控制信号进行切换控制而改变.因此,锁相环的特性,诸如环路带宽等,也可通过电流的改变而改变.采用具有初始化电路的环路滤波器可提高锁相环的启动速度.另外采用了多模频率除法器以实现频率合成的功能.该电路采用0118Λ118V、1P6m、M标准数字CMOS工艺实现.

关键词:锁相环;电荷泵;滤波器;多模频率除法器

EEACC:2570

中图分类号:TN43112　　　文献标识码:A　　　文章编号:025324177(2003)1221244206

3上海市应用材料基金资助项目(No.0102)

　赵　晖　男,1969年出生,博士研究生,研究兴趣为CMOS模拟及射频前端集成电路设计.　任俊彦　男,1960年出生,教授,研究兴趣为射频前端电路和计算机通信电路的设计.　章倩苓　女,1936年出生,教授,研究兴趣为微电子、片上系统设计.　2003205202收到,2003207204定稿

c2003中国电子学会○

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