按键扫描与LED显示驱动芯片ET6218R芯片资料

Etek

Microelectronics ET6218R

LED Controller/driver

General Description

ET6218R is an LED Controller driver on a 1/7 to 1/8 duty factor. 7 segment output lines, 4 grid output lines, 1 segment/grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to ET6218R via a three-line serial interface, ET6218R pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages.

Features

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CMOS Technology

Low Power Consumption

Multiple Display Modes(4～5 Grid, 7～8 segment) Key scaning(7×1 Matrix) 8-step Dimming Circuitry

Serial Interface for Clock, Data Input/Output, Strobe Pins Available in 18-pin, DIP Package

Pin Configurations

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Pin Description

Pin No.

Pin Name

I/O

Description

Data I/O Pin(N-channel, Open-Drain)

This pin outputs serial data at the falling edge of the shift clock and

5 DI/O(DIN&DOUT) I/O inputs serial data at the rising edge of the shift clock(starting from the lower bit)

Clock Input Pin

6 CLK I This pin reads serial data at the rising edge and outputs data at the

falling edge

Serial Interface Strobe Pin

7 STB I The data input after the STB has fallen is processed as a command

When this pin is “HIGH”, CLK is ignored Key Data Input Pins

8 K1 I The data sent to these pins are latched at the end of the display cycle

(Interface Pull-Low Resistor)

2 GND ─ Ground Pin

Segment Output Pins(p-channel, open drain) Also acts as the Key SG1/KS1～

10~16 O Source SG7/KS7 17 SG14/GR5 O Segment/Grid Output Pins 9 VDD ─ Power Supply 1,3,4,18 O Grid Output Pins GR4～GR1 INPUT/OUTPUT CONFIGURATIONS

The schematic diagrams of the input and output circuits of the logic section are shown below. 1. Input Pins：CLK，STB&DIN(DI/O)

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2. Input Pins：K1

VDDGND 3. Output Pins：DOUT(DI/O)，GR1～GR4

VDDGND 4. Output Pins：SG1～SG7

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5. SG14/GR5

VDDGND Block Diagram

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Functional Description

COMMANDS

A command is the first byte(b0～b7) inputted to ET6218R via the DI/O Pin after STB Pin has changed from HIGH to LOW State. If for some reason the STB Pin is set to HIGH while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid.

Command 1：Display Mode Setting Commands

ET6218R provides 2 display mode settings as shown in the diagram below：As started earlier a command is the first one byte(b0～b7) transmitted to ET6218R via the DI/O Pin when STB is LOW. However, for these commands,the bit 3 to bit 6(b2～b5)are ignored,bit 7&bit 8(b6～b7) are given a value of 0.

The Display Mode Setting Commands determine the number of segments and grids to be used (7 to 8 segments,4 to 5 grids). A display command ON must be excuted in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned ON,the 7-grid, 10-segment modes is selected.

MSB LSB 0 0 ─ ─ ─ ─ b1 b0 b2～b5：Not Relevant Display Mode Setting：

b1,b0—0 0：4 Grids,8 Segments b1,b0—0 1：5 Grids,7 Segments

Command 2:Data Setting Commands

Data Setting Commands executes the Data Write or Data Read Modes for ET6218R. The data Setting Command, the bits 5 and 6(b4,b5) are ignored, bit 7(b6) is given the value of 1 while bit 8(b7) is given the value of 0. Please refer to the diagram below. When Power is turned ON, bit 4 to bit 1(b3～b0) are given the value of 0. MSB LSB 0 1 b1 b0 ─ ─ b3 b2 b4,b5：Not Relevant

Mode Setting： b3 —0：Normal Operation Mode b3—1：Test Mode

Address Increment Mode Settings(Display Mode)： b2—0：Increment Address after Data has been Written b2—1：Fixes Address

Data Write&Read Mode Setting：

b1,b0—0 0：Write Data to Display Mode b1,b0—1 0：Read Key Data

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ET6218R KEY MATRIX&KEY INPUT DATA STORAGE RAM ET6218R Key Matrix consists of 7×1 array as shown below：

Each data entered by each key is stored as follows and read by a READ Command, starting from the last significant bit of the next data(b7) is read. K1 K1 x x x x READINGSEQUENCESG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 b0 b3 b6 Note：b6 do not care.

Command 3：Address Setting Commands

Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of 00H to 0DH. If the address is set to 0EH or higher,the data is ignored until a valid address is set. When power is turned ON,the address is set at 00H.

MSB LSB 1 1 b1 b0 ─ ─ b3 b2 b4,b5：Not Relevant

The address of b3～b0：00H～0DH

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DISPLAY MODE AND RAM ADDRESS

Data transmitted from an external device to ET6218R via the interface are stored in the Display RAM and are assigned address. The RAM addresses of ET6218R are given below in 8 bits unit.

SG1…………SG4 SG5…………SG8 SG9…………SG12SG13…………SG14

00HL 00HU 01HL 01HU DIG1 02HL 02HU 03HL 03HU DIG2 04HL 04HU 05HL 05HU DIG3 06HL 06HU 07HL 07HU DIG4 08HL 08HU 09HL 09HU DIG5

b0…………….b3 b4………………b7

xxHL xxHU Lower 4 bits Higher 4 bits

Command 4：Display Control Commands

The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON,a 1/16 pulse width is selected and the displayed is turned OFF(the key scaning is stopped).

MSB LSB 1 0 b1 b0 ─ ─ b3 b2 b4,b5 ：Not Relevant

Display Setting： b3—0：Display OFF(Key Scan Continues) b3—1：Display ON

Dimming Quantity Setting： 000：Pulse width=1/16 001：Pulse width =2/16 010：Pulse width =4/16 011：Pulse width =10/16 100：Pulse width =11/16 101：Pulse width =12/16 110：Pulse width =13/16 111：Pulse width =14/16

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SCANNING AND DISPLAY TIMING

The Key Scanning and Display Timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the are 7×1 matrix is stored in the RAM. Tdisplay=500usKey Scan DataSG OutputDIG1DIG2DIG3DIGnDIG1G1G2G3Gn1frame=Tdisplay ×（n+1） Rev 1.0 2012-4-13

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SERIAL COMMUNICATION FORMAT

The following diagram shows the ET6218R serial communication format.The DI/O(DIN,DOUT) Pin is an N-channel,open-drain pin, therefore, it is highly recommended that an external pull-up resistor(1K～10K) must be connected to DI/O.

Reception(Data/Command Writer) If data continuesSTBDINb0b1b2b6b7CLK12378 Transmission(Data Read) STB DINb0b1b2b3b4b5b6b7CLK12345678twait123456DOUTb0b1b2b3b4b5Data Read Command is setData Reading startstwait(waiting time)≥1µs It must be noted that when the data is read, the waiting time(twait) between the rising of the eighth clock that has set the command and the galling of the first clock that has read the data is greater or equal to 1µs.

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SWITCHING CHARACTERISTIC WAVEFORM

ET6218R Switching Characteristics Waveform is given below. foscOSC50%PWSTBSTBPWCLKCLKPWCLKtCLK-STBtsetuptholdDINtPZLtPLZDOUTtTZLGn90%tTLZ10%10%90%SntTZHtTHZ PWCLK（Clock Pulse Width）≥400ns PWSTB（Strobe Pulse Width）≥1µs tsetup（Data Setup Time）≥100ns thold（Data Hold Time）≥100ns tCLK-STB（Clock-Strobe Time）≥1µs tTHZ（Fall Time）≤10µs

tTZH（Rise Time）≤1µs tPZL（Propagation Delay Time）≤100ns fosc=Ocillation Frequency tPLZ（Propagation Delay Time）≤300ns tTZL<1µs tTLZ<10µs

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Note：Test condition under

tTHZ（Pull low risistor=10kΩ，Loading capacitor=300pf） tTLZ（Pull low risistor=10 kΩ，Loading capacitor =300pf）

APPLICATION

1. Display memory is updated by incrementing addresses. Please refer to the following diagram. STBCLKDINCommand2Command3Data1Data nCommand1Command4 Command 1：Display Mode Setting Command Command 2：Data Setting Command Command 3：Address Setting Command

Data 1～n：Transfer Display Data(14 Bytes max) Command 4：Display Control Command

2. The following diagram shows the waveform when updating specific addresses. STBCLKDINCommand2Command3DataCommand3Data Command 2：Data Setting Command Command 3：Address Setting Command Data：Display Data

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RECOMMENDED SOFTWARE PROGRAMMING FLOWCHART STARTDelay 200 msSETCOMMAND2(Writer Data)SETCOMMAND3Clear Display RAM(See Note 5)SETCOMMAND1INITIALSETCOMMAND4(88H-87H：Display OFF)SETTINGSETCOMMAND1SETCOMMAND4(88H-8FH：Display ON)MAIN PROGRAMSETCOMMAND2(READ KEY & WRITER DATA INCLUDED)MAINSETCOMMAND3LOOPSETCOMMAND1SETCOMMAND4END Rev 1.0 2012-4-13

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Note：1. Command 1：Display Mode Commands

2. Command 2：Data Setting Commands 3. Command 3：Address Setting Commands 4. Command 4：Display Control Commnads

When IC power is applied for the first time, the contents of the Display RAM is not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting.

Absolute Maximum Ratings（Ta = 25℃，GND = 0V）

Parameter Supply Voltage Logic Input Voltage Driver Output Current

Maximum Driver Output Current/Total

Operating Temperature Storage Temperature

Symbol Ratings Unit VDD V -0.5～+7 VI V -0.5～VDD+0.5

mA IOLGR +250 IOHSG -50 mA ITOTAL 400 mA Topr -40～+85 ℃ Tstg -55～+150 ℃

Recommended Operating Range（Ta = -20～+70℃，GND = 0V）

Parameter Symbol Min. Typ. Max. Unit

Logic Supply Voltage VDD 3 5 5.5 V Dynamic Current(see Note)IDDdyn 5 mA — — High-Level Input Voltage VIH 0.6VDD VDD V — Low- Level Input Voltage VIL 0 — 0.3VDD V Note：Test Condition：Set Display Control Commands=80H(Display Turn OFF State&under no load)

Electrical Characteristics（VDD = 5V，GND = 0V，Ta = 25℃）

Parameter

High-Level Output Current

IOHSG2

Low-Level Output Current Low-Level Output Current Segment High-Level Output Current Tolerance High-Level Input Voltage Low-Level Input Voltage Oscillation Frequency K1 Pull Down Resistor

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Symbol IOHSG1

IOLGR IOLDOUT ITOLSG VIH VIL fosc

RKN

Test Condition

VO =VDD-2V，SG1～SG7,

SG14

VO =VDD-3V，SG1～SG7,

SG14

VO =0.3V，GR1～GR5,

VO =0.4V

VO =VDD-3V，SG1～SG7,

SG14

— —

Min. Typ. Max.Unit

-20 -25 -40 mA -25 -30 -50 mA 100 140 — 4 — — — 0.6 VDD 0

—

mA mA

+5 % — 5 V —

0.3

V

VDD

350 500 650 kHz

= VDD5V 40 100 kΩ —

ET6218R

（VDD=3V, GND=0V, Ta=25℃）

Parameter Symbol High-Level Output Current Low-Level Output Current

Low-Level Output Current Segment High-Level Output Current Tolerance High-Level Input Voltage Low-Level Input Voltage Oscillation Frequency K1 Pull Down Resistor

Test Condition Min. Typ. Max.UnitVO= VDD -2V，SG1～SG7,

IOHSG1 -15 -20 -35 mA SG14

IOLGR VO=0.3V，GR1～GR5, 100 140 — mA IOLDOUT =VO0.4V 4 — — mA VO= VDD -3V，SG1～SG7,

ITOLSG % — — +5

SG14

0.8

VIH 3.3 V — —

VDD

0.3VD

VIL — 0 — V

D

fosc 300 420 580 kHz RKN VDD =3V 40 100 kΩ —

Application Circuit

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COMMON CATHODE TYPE LED PANEL

Note ：

1. The capacitor(0.1µF)connected between the GND and VDD pins must be located as close as possible to the ET6218R chip.

Package Dimension

DIP 18 3.10～3.503.00min1.524TYP2.54TYP0.51minAA7.62TYPSECTION A-AKWith PlatingK1J1J10°max22.70～23.10Base Metal6.30～6.70DimJJ1KK1Min0.2190.2190.460.46Max0.3390.20.560.51Unit：mm Rev 1.0 2012-4-13

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