AT91C140-CI资料

•ARM7TDMI® ARM® Thumb® Processor Core•

–In-Circuit Emulator, 36 MHz OperationEthernet Bridge

–Dual Ethernet 10/100 Mbps MAC Interface–16-Kbyte Frame Buffer

1 K-Byte Boot ROM, Embedding a Boot Program–Enable Application Download from DataFlash®External Bus Interface

–On-chip 16-bit SDRAM Controller

–4 Chip Select Static Memory Controller

Multi-level Priority, Individually Maskable, Vectored Interrupt ControllerThree 16-bit Timer/Counters

Two UARTs with Modem Control LinesSerial Peripheral Interface (SPI)

Two PIO Controllers, Managing up to 48 General-purpose I/O PinsAvailable in a 208-lead PQFP PackagePower Supplies

–VDDIO 3.3V nominal

–VDDCORE and VDDOSC 1.8V nominal-40°C to + 85°C Operating Temperature Range

••

•••••••

AT91 ARM® Thumb® MicrocontrollersAT91C140 Summary•

1.Description

The AT91C140 is a member of the Atmel AT91 16- and 32-bit microcontroller family based on the ARM7TDMI processor core. This processor has a high performance 32-bit RISC architecture with a high density 16-bit instruction set and very low power consumption.

In addition, the AT91C140 integrates a double Ethernet 10/100 base-T MAC capable of operating as an Ethernet bridge, thus making it ideally suited for networking appli-cations. It supports a wide range of memory devices such as SDRAM, SRAM and Flash and embeds an extensive array of peripherals.

The device is manufactured using Atmel’s high-density CMOS technology. By com-bining the ARM7TDMI processor core with an expansive assortment of peripheral functions and low-power oscillator and PLL on a monolithic chip, the Atmel AT91C140 is a powerful microcontroller that provides a highly flexible and cost effective solution to many networking applications.

6069CS–ATARM–15-Sep-05Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.

2.Block Diagram

Figure 2-1.

AT91C140 Block Diagram

JTAG Debug InterfaceICEARM7TDMI ProcessorBoot ROMExternal Bus InterfaceMII PHY InterfaceEthernet10/100 Mbps MAC InterfaceASB/ASBBridgeSDRAMC16-bit Data Memory BusMII PHY InterfaceEthernet10/100 Mbps MAC Interface32k BytesSRAMSMCPeripheral BridgeOSCPLLInterrupt and Fast InterruptAdvanced InterruptControllerPeripheral DataControllerSystem ControllerSPISerial PeripheralsBoot DataFlashUSART ASerial PortUSART BI/O LinesPIO Controller ATimer/Counter 0I/O LinesPIO Controller BTimer/Counter 1Timer/Counter 2Serial PortPWM SignalsPWM SignalsPWM Signals 2

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

3.Pinout

Table 3-1.

Pinout for 208-lead PQFP Package

Pin

Pin

Pin

Number

Signal Name

Number

Signal Name

Number

Signal Name

1GND37MB_TXD073A152GND38MB_TXD174A163VDDIO39MB_TXD275A174GND40GND76A185NC(1)41MB_TXD377A19B/A06GND42MB_TXEN78A20/BA17NTRST43MB_TXCLK79A218MA_COL44MB_RXD080D09MA_CRS45MB_RXD181D110MA_TXER46MB_RXD282D211MA_TXD047MB_RXD383D312MA_TXD148MB_RXER84GND13MA_TXD249MB_RXCLK85D414MA_TXD350MB_RXDV86VDDIO15MA_TXEN51MB_MDC87D516VDDIO52VDDIO88D617MA_TXCLK53GNDD718GND54MB_MDIO90D819MA_RXD055MB_LINK91D920MA_RXD156A092D1021MA_RXD257A193D1122MA_RXD358A294D1223MA_RXER59A395D1324MA_RXCLK60A496D1425GND61A597VDDCORE26VDDCORE62A698GND27MA_RXDV63A799D1528MA_MDCA8100VDDIO29MA_MDIO65A9101GND30MA_LINK66A10102VDDIO31MB_COL67A11103NC(1)32MB_CRS68A12104VDDIO33GND69VDDIO105GND34VDDCORE70GND106SDCK35VDDIO71A13107SDCS36

MB_TXER

72

A14

108

SDA10

6069CS–ATARM–15-Sep-05

Pin

Number

Signal Name

109RAS110CAS111NC(1)112WE113DQM0114DQM1115NC(1)116GND117NC(1)118VDDCORE119GND120VDDOSC121PLLRC122GND123GND124XTALOUT125XTALIN126VDDCORE127NCE0128NCE1129NCE2130VDDIO131NCE3132NWE0133NWE1134NC(1)135VDDIO136GND137NC(1)138NWR139NSOE140GND141VDDCORE142VDDIO 143MISO144

MOSI

3

Table 3-1.

Pin

Number

145146147148149150151152153154155156157158159160

Pinout for 208-lead PQFP Package (Continued)

Signal Name

SPCKPA22VDDIOGNDNRSTFIQIRQ0TSTGNDVDDCORENC(1)VDDIOGNDVDDIOTDOTDI

Pin

Number

1611621631165166167168169170171172173174175176

Signal Name

TMSTCKPA19VDDCOREGNDPA12GNDVDDIOPA11PA10PA9PA8PA7PA6VDDIONC(1)

Pin

Number

1771781791801811821831841851861871881190191192

Signal Name

PA5PA4PA3PA2PA1PA0GNDRXDATXDANRSTANCTSANDTRANDSRANDCDARXDBTXDB

Pin

Number

193194195196197198199200201202203204205206207208

Signal Name

GNDPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9VDDIOGNDGNDGNDVDDIO

Note:1.NC leads should be left unconnected.

4

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

4.Signal Description

Table 4-1.

Block

Signal Description

Signal NameVDDIO

Function

I/O Lines Power SupplyDevice Core Power SupplyPLL and Oscillator Power SupplyGroundAddress BusData BusSDRAM ClockSDRAM Byte MasksSDRAM Chip Select SDRAM Address Line 10Row Address StrobesColumn Address StrobesWrite EnableBank Address LineChip Selects

Byte Select/Write EnableOutput Enable

Memory Block Write EnablePIO Controller A I/O Lines PIO Controller B I/O Lines Timer Counter Clock 0 to 2Timer Counter I/O Line A 0 to 2Timer Counter I/O Line B 0 to 2Master In/Slave OutMaster Out/Slave InSerial Clock

Peripheral Chip Select 0/Slave SelectPeripheral Chip Select 1 to 3

OutputInput/OutputOutputOutputOutputOutputOutputOutputOutputOutputOutputOutputOutputOutputInput/OutputInput/Output

InputInput/OutputInput/OutputInput/OutputInput/OutputInput/OutputInput/OutputOutputType

Power Supplies

VDDCOREVDDOSCGND

External Bus Interface

A0-A23D0-D15SDCKDQM0-DQM1SDCS

Synchronous Dynamic Memory Controller

SDA10RASCASWEBA0-BA1NCE0-NCE3

Static Memory Controller

NWE0-NWE1NSOENWR

PIO Controller APIO Controller B

PA0-PA12, PA19, PA22PB0-PB9TCLK0-TCLK2

Timer CounterTIOA0-TIOA2TIOB0-TIOA2MISOMOSI

Serial Peripheral InterfaceSPCKNPCS0/NSSNPCS1-NPCS3

5

6069CS–ATARM–15-Sep-05

Table 4-1.

Block

Signal Description (Continued)

Signal NameRXDA-RXDBTXDA-TXDBNRTSA-NRSTBNCTSA-NCTSB

FunctionReceive DataTransmit DataReady to SendClear to SendData Terminal ReadyData Set ReadyData Carrier DetectRing IndicatorUART Serial ClockMAC A Collision DetectMAC A Carrier SenseMAC A Transmit ErrorMAC A Transmit Data BusMAC A Transmit EnableMAC A Transmit ClockMAC A Receive Data BusMAC A Receive ErrorMAC A Receive ClockMAC A Receive Data ValidMAC A Management Data ClockMAC A Management Data BusMAC A Link InterruptMAC B Collision DetectMAC B Carrier SenseMAC B Transmit ErrorMAC B Transmit Data BusMAC B Transmit EnableMAC B Transmit ClockMAC B Receive Data BusMAC B Receive ErrorMAC B Receive ClockMAC B Receive Data ValidMAC B Management Data ClockMAC B Management Data BusMAC B Link Interrupt

TypeInputOutputOutputInputOutputInputInputInputI/OInputInputOutputOutputOutputInputInputInputInputOutputOutputInput/Output

InputInputInputOutputOutputOutputInputInputInputInputOutputOutputInput/Output

Input

UART A and UART BNDTRA-NDTRBNDSRA-NDSRBNDCDA-NDCDBNRIA-NRIBSCKAMA_COLMA_CRSMA_TXER

MA_TXD0-MA_TXD3MA_TXENMA_TXCLK

MAC A InterfaceMA_RXD0-MA_RXD3MA_RXERMA_RXCLKMA_RXDVMA_MDCMA_MDIOMA_LINKMB_COLMB_CRSMB_TXER

MB_TXD0-MB_TXD3MB_TXENMB_TXCLK

MAC B InterfaceMB_RXD0-MB_RXD3MB_RXERMB_RXCLKMB_RXDVMB_MDCMB_MDIOMB_LINK

6

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

Table 4-1.

Block

Signal Description (Continued)

Signal NameNTRSTTCK

FunctionTest ResetTest ClockTest Mode SelectTest Data InputTest Data OutputResetFast InterruptInterrupt LinesPLL RC FilterCrystal InputExternal Crystal Test ModeARM Clock Output

TypeInputInputInputInputOutputInputInputInputAnalogAnalogAnalogInputOutput

In-Circuit EmulatorTMSTDITDONRSTFIQIRQ0-IRQ1

Miscellaneous

PLLRCXTALINXTALOUTTSTACLKO

7

6069CS–ATARM–15-Sep-05

5.Functional Description

5.1

ARM7TDMI Core

The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bit wide and give maximum code density.Instructions operate on 8-bit, 16-bit and 32-bit data types.

The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six sta-tus registers.

5.2Ethernet MAC

The AT91C140 features two identical Ethernet MACs with the same attributes as follows:•Compatible with IEEE Standard 802.3

•10 and 100 Mbits per Second Data Throughput Capability•Full- and Half-duplex Operation

•Media Independent Interface to the Physical Layer

•Register Interface to Address, Status and Control Registers•DMA Interface

•Interrupt Generation to Signal Receive and Transmit Completion•28-byte Transmit and 28-byte Receive FIFOs

•Automatic Pad and CRC Generation on Transmitted Frames•Address Checking Logic to Recognize Four 48-bit Addresses

•Supports Promiscuous Mode Where All Valid Frames are Copied to Memory•Supports Physical Layer Management through MDIO Interface

The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data frame for-mat. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management. The Ethernet MAC transfers data in media-independent interface (MII).

5.3Peripheral Multiplexing on PIO Lines

The AT91C140 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the peripheral set.

The PIO Controller A manages 32 I/O lines, PA0 to PA31, but only the I/O lines PA0 to PA12 PA19 and PA22 are available in the 208-lead package.

The PIO Controller B manages only 16 I/O lines, PB0 to PB15, but only the I/O lines PB0 to PB9 are available in the 208-lead package.

Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O.

8

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

5.4

Power Supplies

The AT91C140 has three types of power supply pins:

•VDDCORE pins power the core, including the ARM7TDMI processor, the memories and the peripherals; voltage is between 1.65V and 1.95V, 1.8V nominal.

•VDDIO pins power the I/O lines, including those of the External Bus Interface and those of the peripherals; voltage is between 3.0V and 3.6V, 3.3V nominal.

•VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and 1.95V, 1.8V nominal.

Ground pins are common to all power supplies.

5.5System Controller

The AT91C140 features a System Controller, which takes care of and controls:•The Test Mode•TheReset

•The Clocks of the System•The Chip Identifier

The System Controller manages the reset of the entire system and integrates a clock genera-tor made up of an oscillator and a PLL.

5.6Memory Controller

The AT91C140 architecture is made up of two Advanced System Buses, the ARM ASB and the MAC ASB. Both handle a single memory space.

The ARM ASB handles the access requests of the ARM7TDMI and the PDC. It handles also the access requests coming from the MAC ASB. It connects with the External Bus Interface, the Peripheral Bridge and the Internal Memories. It also connects with the MAC ASB.

The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also han-dles the access requests coming from the the ARM ASB. It connects essentially with the Frame Buffer, but also connects with the ARM ASB.

The major advantage of this double-ASB architecture is that the Ethernet traffic does not occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maximum speed while the Ethernet traffic goes through the Frame Buffer.

5.7Boot Program

The AT91C140 can boot in several ways; including from internal boot software and a hard-ware connection of DataFlash. When the ARM7TDMI processor is released from reset, it basically attempts a fetch from address 0x00000000. Depending on the hardware configura-tion, the memory mapping can be altered and thus modify how the system boots.

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6069CS–ATARM–15-Sep-05

6.Peripherals

The Peripheral Bridge allows access to the embedded peripheral user interfaces. It is opti-mized for low power consumption, as it is built without usage of any clock. However, any access on the peripheral is performed in two cycles.

The AT91C140 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the address space.

6.1PDC: Peripheral Data Controller

The AT91C140 features a six-channel Peripheral Data Controller (PDC) dedicated to the two on-chip UARTs and the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each UART and of the SPI.Each PDC channel operates as DMA (Direct Memory Access).

The User Interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible in the peripheral status register. This status bit might trigger an interrupt.

6.2EBI: External Bus Interface

The External Bus Interface generates the signals which control access to external memories or peripheral devices. It contains two controllers: the SDRAM Controller and the Static Mem-ory Controller and manages the sharing of data and address buses between both controllers.

6.3SDRAMC: SDRAM Controller

The SDRAM Controller extends the memory capabilities of a chip by providing the interface to an external 16--bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The maximum addressable SDRAM size is 256M bytes.

The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advis-able to avoid accessing different rows in the same bank.

The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user.

6.4SMC: Static Memory Controller

The AT91C140 features a Static Memory Controller that enables interfacing with a wide range of external static memory on peripheral devices, including Flash, ROM, static RAM, and paral-lel peripherals.

The SMC provides a glueless memory interface to external memory using common address, data bus and dedicated control signals. The SMC is highly programmable and has up to 24 bits of address bus, a 16-bit data bus and up to four chip select lines. The SMC supports differ-ent access protocols allowing single clock-cycle accesses. The SMC is programmed as an internal peripheral that has a standard APB bus interface and a set of memory-mapped regis-ters. It shares the external address and data buses with the SDMC.

10

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

6.5

AIC: Advanced Interrupt Controller

The AT91C140 integrates an Advanced Interrupt Controller (AIC) which is connected to the fast interrupt request (nFIQ) and the standard interrupt request (nIRQ) inputs of the ARM7TDMI processor. The processor’s nFIQ line can only be asserted by the external fast interrupt request input (FIQ). The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the two external interrupt request lines, IRQ0 to IRQ1.

An 8-level priority encoder allows the user to define the priority between the different interrupt sources. Internal sources are programmed to be level-sensitive or edge-triggered. External sources can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive.

6.6PIO: Programmable I/O Controller

The AT91C140 integrates two PIO controllers, PIOA and PIOB. PIOA controls 15 I/O lines and PIOB controls 10 I/O lines. Each I/O line can be programmed as an input or an output and can generate an interrupt on level change.These pins are used for several functions:•External I/O for internal peripherals•Keypad controller function•General-purpose I/O

6.7UART: Universal Asynchronous Receiver Transmitter

The AT91C140 provides two identical full-duplex, Universal Asynchronous Receiver Transmit-ters as UART A and UART B. These peripherals sit on the APB bus but are also connected to the ASB bus (and hence external memory) via a dedicated DMA.The main features of the UART are:•Programmable Baud Rate Generator•Parity, Framing and Overrun Error Detection•Line Break Generation and Detection

•Automatic Echo, Local Loopback and Remote Loopback Channel Modes•Interrupt Generation

•Two Dedicated Peripheral Data Controller Channels•6-, 7- and 8-bit Character Length•Modem Control Signals

6.8TC: Timer/Counter

The AT91C140 features a timer/counter block which includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation.

Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate processor interrupts via the AIC.The timer/counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same

11

6069CS–ATARM–15-Sep-05

instruction. The Block Mode Register defines the external clock inputs for each timer/counter channel, allowing them to be chained.

6.9SPI: Serial Peripheral Interface

The Serial Peripheral Interface circuit is a synchronous serial data link that provides communi-cation with external devices in Master or Slave Mode. It also allows communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPI's. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other system acts as the “slave'' which has data shifted into and out of it by the master. Different CPU's can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time.The main features of the SPI are:

•Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals

•Serial Memories, such as DataFlash and 3-wire EEPROMs

•Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors•External Coprocessors

•Master or Serial Peripheral Bus Interface

•8- to 16-bit Programmable Data Length Per Chip Select •Programmable Phase and Polarity Per Chip Select

•Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select

•Programmable Delay Between Consecutive Transfers•Selectable Mode Fault Detection

•Connection to PDC Channel Capabilities Optimizes Data Transfers•One Channel for the Receiver, One Channel for the Transmitter

12

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

7.Mechanical Characteristics and Packaging

7.1

PQFP Packaging Information

Figure 7-1.AT91C140 PQFP Package For PQFP package data, see Table 7-1 on page 14,

6069CS–ATARM–15-Sep-05

13

7.2PQFP Package Data

Table 7-1.

AA1A2

0.253.20

3.32

3.60

Package Dimensions for 208-lead PQFP Package (in mm)

Min

Nom

Max4.10

Symbol

DD1EE1R2R1QQ1Q2Q3cLL1SbeD2E2

0.200.170.110.730.130.130°0°

31.20 BASIC28.00 BASIC31.20 BASIC28.00 BASIC

0.30

7°

8° Ref8° Ref0.150.881.60 REF

0.231.03

0.200.50 BSC25.5025.50

0.27

Tolerances of form and position

aaabbbccc

0.250.200.08

0.0100.0080.003

14

AT91C140 Summary

6069CS–ATARM–15-Sep-05

AT91C140 Summary

8.Ordering Information

Table 8-1.

Ordering Information

PackagePackage Type

Temperature Operating Range

Ordering CodeAT91C140-QU-001

PQFP208

Green

6069CS–ATARM–15-Sep-05

-40°C to +85°C

15

Revision History

Doc. Rev.6069AS6069BS

Date19-Apr-0416-May-05

CommentsFirst issue.

Changed package to PQFP208. Updated ordering information.Global, External Bus Interface references to 32-bit changed to 16-bit or removed.

Table 3-1, “Pinout for 208-lead PQFP Package,” DBW32 and BO256 changed to GND

Table 4-1, “Signal Description,” DBW32 removedGlobal all instances of the following changed DQM0-DQM3 changed to DQM0-DQM1NWE0-NWE3 changed to NWE0-NWE1

External Bus interface D0-D31 changed to D0-D15

Table 3-1, “Pinout for 208-lead PQFP Package,” Replaced SCLKA, FSA, STXA, SRXA by GND or NC

Table 4-1, “Signal Description,” SCKA added to UART descriptionPIO descriptions changed.

CSR 04-420, 05-155CSR 05-403

Change Request Ref.

6069CS01-Sep-05

CSR 05-409 HIi

16

AT91C140 Summary

6069CS–ATARM–15-Sep-05

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